1. Field of the Invention
The present invention relates to a semiconductor integrated circuit adapted to output the PASS/FAIL results of internal operations to the outside of the semiconductor chip. Specifically, the present invention relates to a nonvolatile semiconductor storage device, such as a NAND-cell EEPROM, a NOR-cell EEPROM, a DINOR-cell EEPROM, or an AND-cell EEPROM.
2. Description of the Related Art
An electrically rewritable EEPROM is known as one type of semiconductor storage device. In particular, a NAND-cell-based EEPROM in which a plurality of memory cells are connected in series to form a NAND cell block has attracted a great deal of attention because of its adaptability for high packing densities.
One memory cell in the NAND-cell-based EEPROM has an FET-MOS structure in which a floating gate (charge storage layer) and a control gate are formed over the semiconductor substrate such that the former is located below the latter with an insulating film interposed therebetween. A plurality of memory cells are connected in series such that the source of each cell is common to the drain of the adjacent cell, thereby forming a NAND cell. The NAND cell is connected as a unit to a corresponding bit line.
Such NAND cells are arranged in a matrix form to constitute a memory cell array. The memory cell array is manufactured into a p-type well (or a p-type substrate). NAND cells arranged in the column direction of the memory cell array have their respective drains at their one end connected together through select gate transistors to a corresponding bit line and their respective sources at their other end connected together through select gate transistors to a common source line.
The control gates of memory cell transistors arranged in the row direction of the memory cell array are connected together to form a control gate line (word line). Likewise, the gates of the select gate transistors arranged in the row direction are connected together to form a select gate line.
The NAND-cell EEPROM operates in the following manner:
Data program operation begins with the memory cell located furthest from a bit line contact. The control gate of the selected memory cell is supplied with a high voltage Vpgm of about 18 V. The control gates of the memory cells located nearer the bit line contact and the select gates are supplied with an intermediate voltage Vmw of about 10 V. The bit line is supplied with 0 V or an intermediate voltage of about 8 V according to data.
When the bit line is supplied with 0 V, the voltage is transferred to the drain of the selected memory cell, so that tunneling of electrons from the drain into the floating gate occurs. Thereby, the threshold voltage of the selected memory cell is caused to shift in the positive direction. This state is assumed to be “0” by way of example.
When the intermediate voltage Vmb is applied to the bit line, no tunneling of electrons occurs and hence the threshold voltage of the memory cell is not changed and remains negative. This state corresponds to “1”.
Data erasing is performed simultaneously on all the memory cells in a selected NAND cell block. That is, all the control gates in the selected NAND cell block are set at 0 V, a high voltage Vera of about 22 V is applied to the p-type well (or the p-type substrate). The bit and source lines and the control gates in nonselected NAND cell blocks and all the select gate lines are rendered floating.
Thereby, in all the memory cells in the selected NAND cell block, electrons in the floating gates due to the tunnel effect are released into the p-type well (or the p-type substrate). Thereby, after erasing, the threshold voltage is shifted in the negative direction.
To read data, the control gate of the selected memory cell is set at 0 V with the control gates of other memory cells and the select gates supplied with the supply voltage Vcc or a read voltage VH higher than Vcc. This read voltage VH is normally less than twice the supply voltage Vcc, say, less than 5 V. In this state, data is sensed by detecting whether or not a current is flowing in the selected memory cell.
FIG. 1 shows example arrangements of the memory cell array and the bit line control circuit of a conventional NAND-cell EEPROM.
In FIG. 1, the memory cell array has 33,792 bit lines BL0 to BL33791 and 1,024 blocks Block0 to Block1023 and row decoders are placed on opposite sides of the array in the row direction.
A sense latch circuit 31 is connected between a pair of bit lines BLi and BLi+1 (i=0, 1, . . . ) and a pair of input/output lines IO and /IO over which data is transferred between the memory array and the data input/output buffer. That is, a single sense latch is connected between the paired input/output lines IO and /IO and each pair of odd- and even-numbered bit lines.
FIG. 2 shows an algorithm for the data program sequence in the NAND cell EEPROM of FIG. 1.
According to this algorithm, data is programmed into each of two or more pages in sequence. While data is being programmed in, that is, when the sense latch circuit 31 is in operation, it cannot be used for another operation, such as data entry.
That is, the data program sequence involves an operation of entering data to be programmed (program data) and an operation of programming data for one page. These operations are performed alternately for each page. That is, the data entry operation cannot be performed concurrently with the data program operation.
Thus, the data entry operation and the data program operation are repeated alternately during the data program sequence. The overall time of the data program sequence is defined mainly by the sum of the time required to enter data and the time required to program data and will therefore become considerably long.
FIG. 3 shows an algorithm for the data read sequence in the NAND-cell EEPROM of FIG. 1.
In this algorithm, each of pages is subjected in sequence to a data read operation. While data is being read, the sense latch circuit 31 is in operation (i.e., in use); thus, it cannot be used for another operation (such as outputting data).
With the algorithm of FIG. 3, the overall time of the data read sequence is determined by the sum of the time required to read data and the time required to output data and will therefore become considerably long.
With a conventional nonvolatile semiconductor storage device such as of the NAND cell type, as described above, it is impossible to perform a data entry operation concurrently with a data program operation and a problem therefore arises in that the overall time of the data program sequence becomes long.
Likewise, it is also impossible to perform a data output operation concurrently with a data read operation and a problem therefore arises in that the overall time of the data read sequence becomes long.